A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment
Résumé
The Self-timed ring based True Random Number Generator (STRNG) leverages the jitter of events propagating in a self-timed ring to generate provably random binary sequences. Several implementations in FPGAs and in CMOS design flows have shown the feasability of this generator in digital technologies, and also confirmed that it can provide high quality random bit sequences that pass the standard statistical test batteries at rates as high as 200 Mbit/s. Following AIS31 recommandations for the design and evaluation of TRNGs, the security of this generator is based primarily on an entropy assessment obtained by modeling the entropy extraction and measuring the entropy source. Secondly, the generator is protected against active attacks by monitoring its behavior in real-time or on demand. In this demonstration, we illustrate this approach in an Altera Cyclone III implementation of the STRNG. We show how the design is configurated depending on the measurement of the entropy source (the jitter magnitude) in order to guarantee a given minimum entropy rate per output bit. Then, we emulate physical attacks on the generator by willingly manipulating its internal structure in order to demonstrate how the entropy monitoring can detect abnormal behaviors and send the appropriate alarms.