H. Naeimi and A. Dehon, A greedy algorithm for tolerating defective crosspoints in nanoPLA design, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921), 2004.
DOI : 10.1109/FPT.2004.1393250

N. Campregher, P. Y. Cheung, and M. Vasilko, Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.138-148, 2005.
DOI : 10.1145/1046192.1046211

A. Mukherjee, R. Jain, and K. Paul, defect-aware design paradigm for reconfigurable architecture, Emergecing VLSI Technologies and architecures, p.6, 2006.

H. Goel and D. Dance, Yield enhancement challenges for 90 nm and beyond, Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI, pp.262-265, 2003.
DOI : 10.1109/ASMC.2003.1194504

V. Lakamraju and R. Tessier, Tolerating operational faults in cluster-based FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays , FPGA '00, pp.187-194, 2000.
DOI : 10.1145/329166.329205

S. Kaneko, A. Doumar, and H. Ito, defect and fault tolerance fpgas by shifting the configuration data, Int l Symp. on Defect and Fault-Tolerance, pp.377-385, 1999.

S. Jose and C. Xilinx, easypath solutions, 2005.

R. Rubin and A. Dehon, choose-your-own-adventure routing: Lightweight load-time defect avoidance [9] Altera Corporation the xilinx isola- tion design flow for fault-tolerant systems, pp.33-33, 2011.

A. B. Dhia, S. Ur-rehman, A. Blanchardon, L. Naviner, M. Benabdenbi et al., a defect-tolerant cluster in a mesh sram-based fpga, FPT, pp.434-437, 2013.
URL : https://hal.archives-ouvertes.fr/hal-01062073

J. Anthony, G. G. Yu, and . Lemieux, fpga defect tolerance: Impact of granularity, the International Conference on Field Programmable Technology, 2005.

E. Amouri, A. Blanchardon, R. Chotin-avot, H. Mehrez, and Z. Marrakchi, Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013.
DOI : 10.1109/ReConFig.2013.6732282

URL : https://hal.archives-ouvertes.fr/hal-00987368

Z. Marrakchi, H. Mrabet, and H. Mehrez, Optimized local interconnect for cluster-based Mesh FPGA architecture, 2008 International Conference on Microelectronics, pp.15-18, 2008.
DOI : 10.1109/ICM.2008.5393494

J. Anthony, G. G. Yu, and . Lemieux, defect tolerant fpga switch block and connection block with fine grain redundancy for yield enhancement, the International Conference on Field Programmable Logic and Application, 2005.

C. Slayman, Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations, Device and Materials Reliability, 2005.
DOI : 10.1109/TDMR.2005.856487

F. Monteiro, S. Piestrak, H. Jaber, and A. Dandache, Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), pp.199-200, 2007.
DOI : 10.1109/IOLTS.2007.32

J. Anthony, G. G. Yu, and . Lemieux, defect tolerant fpga switch block and connection block with fine-grain redundancy for yield enhancement, the International Conference on Field Programmable Logic, 2005.