Energy Efficiency of a Parallel HEVC Software Decoder for Embedded Devices

Abstract : In the context of fast adoption and deployment of recent video compression standard and thanks to recent high performance embedded processors, software video decoding can be performed in real time. But, it becomes among the most energy-intensive applications. Current embedded processors are based on multi-core architecture with advanced convenient features such as Dynamic Voltage Frequency Scaling (DVFS) in order to reduce their power consumption, allowing low power video decoding when no hardware decoding support is available for a given device. This paper deals with energy efficiency impact of different parallelization strategies of a software High Efficiency Video Coding (HEVC) decoder on multi-core ARM big.LITTLE processor. These strategies include the exploitation of data and task-level parallelism, as well as the use of different available DVFS policies.
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https://hal.archives-ouvertes.fr/hal-01154295
Contributor : Erwan Raffin <>
Submitted on : Thursday, May 21, 2015 - 3:21:39 PM
Last modification on : Tuesday, February 5, 2019 - 3:58:15 PM

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Erwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Menard, et al.. Energy Efficiency of a Parallel HEVC Software Decoder for Embedded Devices. Computing Frontiers, May 2015, Ischia, Italy. pp.62:1--62:6, ⟨10.1145/2742854.2747286⟩. ⟨hal-01154295⟩

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