Gate Oxide Degradation of SiC MOSFET in Switching Conditions

Rémy Ouaida (1, 2) , Maxime Berthou (1) , Javier León (3) , Xavier Perpiñà (3) , Sebastien Oge (2) , Pierre Brosselard (1) , Charles Joubert (1)

1 EE - Ampère, Département Energie Electrique
2 Thalès microélectronique
3 CNM - Centre Nacional de Microelectrònica

Under realistic switching conditions, SiC MOSFETs reliability issues remain as a challenge that requires further investigation. In this letter, a specific aging test has been developed to monitor and characterize the electrical parameters of the SiC MOSFET. This allows estimations of the health state and predictions of the remaining lifetime prior to its failure. The gate leakage current seems to be a relevant runaway parameter just before failure. This leakage indicates deterioration of the gate structure. This hypothesis has been validated through analysis of scanning electron microscopy pictures, with a focused ion beam cut showing cracks within the polysilicon.

Mots clés: Silicon carbide; aging test; failure mechanism; oxide degradation; power MOSFET; reliability; switching

Domaines: Energie électrique

Rémy Ouaida, Maxime Berthou, Javier León, Xavier Perpiñà, Sebastien Oge, et al.. Gate Oxide Degradation of SiC MOSFET in Switching Conditions. IEEE Electron Device Letters, 2014, 35 (12), pp.1284 - 1286. ⟨10.1109/LED.2014.2361674⟩. ⟨hal-01154140⟩