Abstract : This paper presents a parallel execution model and a many-core processor design to run C programs in parallel. The model automatically builds parallel sections of machine instructions from the run trace. It parallelizes instructions fetches, renamings, executions and retirements. Predictor based fetch is replaced by a fetch-decode-and-partly-execute stage able to compute in-order most of the control instructions. Tomasulo's register renaming is extended to memory with a technique to match consumer/producer pairs. The Reorder Buffer is adapted to allow parallel retirement. The model is presented on a sum reduction example which is also used to give a short analytical evaluation of the model performance potential.
https://hal.archives-ouvertes.fr/hal-01152664
Contributeur : David Parello
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Soumis le : lundi 18 mai 2015 - 13:42:39
Dernière modification le : jeudi 24 mai 2018 - 15:59:23
Document(s) archivé(s) le : jeudi 20 avril 2017 - 01:51:56
Bernard Goossens, David Parello, Katarzyna Porada, Djallal Rahmoune. Toward a Core Design to Distribute an Execution on a Many-Core Processor. Victor Malyshkin. PaCT: Parallel Computing Technologies, Aug 2015, Petrozavodsk, Russia. Springer International Publishing, 13th International Conference, PaCT 2015, Petrozavodsk, Russia, August 31-September 4, 2015, Proceedings, LNCS (9251), pp.390-404, 2015, Parallel Computing Technologies. 〈10.1007/978-3-319-21909-7_38〉. 〈hal-01152664〉
