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Conference papers
Toward a Core Design to Distribute an Execution on a Many-Core Processor
Abstract : This paper presents a parallel execution model and a many-core processor design to run C programs in parallel. The model automatically builds parallel sections of machine instructions from the run trace. It parallelizes instructions fetches, renamings, executions and retirements. Predictor based fetch is replaced by a fetch-decode-and-partly-execute stage able to compute in-order most of the control instructions. Tomasulo's register renaming is extended to memory with a technique to match consumer/producer pairs. The Reorder Buffer is adapted to allow parallel retirement. The model is presented on a sum reduction example which is also used to give a short analytical evaluation of the model performance potential.
Cited literature [13 references]
https://hal.archives-ouvertes.fr/hal-01152664
Contributor : David Parello <>
Submitted on : Monday, May 18, 2015 - 1:42:39 PM
Last modification on : Wednesday, June 26, 2019 - 5:09:25 PM
Document(s) archivé(s) le : Thursday, April 20, 2017 - 1:51:56 AM
Contributor : David Parello <>
Submitted on : Monday, May 18, 2015 - 1:42:39 PM
Last modification on : Wednesday, June 26, 2019 - 5:09:25 PM
Document(s) archivé(s) le : Thursday, April 20, 2017 - 1:51:56 AM
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submited-pact-2015.pdf
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