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Hardware architecture specification and constraint-based WCET computation

Abstract : The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times.
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Submitted on : Monday, May 4, 2015 - 9:53:50 AM
Last modification on : Thursday, March 18, 2021 - 2:34:40 PM
Long-term archiving on: : Monday, September 14, 2015 - 6:00:23 PM


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  • HAL Id : hal-01148073, version 1
  • OATAO : 12712


Hajer Herbegue, Hugues Cassé, M Filali, Christine Rochange. Hardware architecture specification and constraint-based WCET computation. IEEE International Symposium on Industrial Embedded Systems - SIES 2013, Jun 2013, Porto, Portugal. pp. 259-268. ⟨hal-01148073⟩



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