A hierarchical RF interconnect for MPSoC

Alexandre Brière (1) , Julien Denoulet (1) , Andrea Pinna (1) , Bertrand Granado (1) , François Pecheux (2)

1 SYEL - Systèmes Electroniques
2 CIAN - Circuits Intégrés Numériques et Analogiques

The increasing number of cores in a single chip goes along with the increase of communication needs. To address this issue, we propose a Network on Chip (NoC) using Radio Frequency (RF). We present the detailed architecture of this network and a Multi Processor System on Chip (MPSoC) using it.

Mots clés: Manycore; Hierarchical; Reconfigurable; Network-on-chip; MP SoC; RF; Mpsoc; MPSoCs

Domaines: Architectures Matérielles [cs.AR]; Modélisation et simulation

Alexandre Brière, Julien Denoulet, Andrea Pinna, Bertrand Granado, François Pecheux. A hierarchical RF interconnect for MPSoC. 9ème colloque du GDR SOC-SIP du CNRS, Jun 2014, Paris, France. 2014. ⟨hal-01145448⟩