A hierarchical RF interconnect for MPSoC

Alexandre Brière; Julien Denoulet; Andrea Pinna; Bertrand Granado; François Pecheux

Poster communications

A hierarchical RF interconnect for MPSoC

Alexandre Brière ^{1, *} Julien Denoulet ¹ Andrea Pinna ¹ Bertrand Granado ¹ François Pecheux ²

* Corresponding author

1 SYEL - Systèmes Electroniques

LIP6 - Laboratoire d'Informatique de Paris 6

2 CIAN - Circuits Intégrés Numériques et Analogiques

LIP6 - Laboratoire d'Informatique de Paris 6

Abstract : The increasing number of cores in a single chip goes along with the increase of communication needs. To address this issue, we propose a Network on Chip (NoC) using Radio Frequency (RF). We present the detailed architecture of this network and a Multi Processor System on Chip (MPSoC) using it.

Keywords : MPSoCs Mpsoc RF MP SoC Manycore Hierarchical Reconfigurable Network-on-chip

Document type :

Poster communications

Domain :

Computer Science [cs] / Hardware Architecture [cs.AR]

Computer Science [cs] / Modeling and Simulation

Complete list of metadata

https://hal.archives-ouvertes.fr/hal-01145448
Contributor : Alexandre Brière Connect in order to contact the contributor
Submitted on : Friday, April 24, 2015 - 11:45:25 AM
Last modification on : Tuesday, January 12, 2021 - 9:38:02 AM

A hierarchical RF interconnect for MPSoC

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A hierarchical RF interconnect for MPSoC

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