FoRTReSS: a flow for design space exploration of partially reconfigurable systems

François Duhem (1) , Fabrice Muller (1) , Robin Bonamy (1) , Sebastien Bilavarn (1)

1 LEAT - Laboratoire d'Electronique, Antennes et Télécommunications

In this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is automatically inferred from application resources information, interface constraints and the target device. Real-time constraints are verified by a highly configurable SystemC simulator, RecoSim, handling applications described as control data flow graphs (CDFGs). We demonstrate our approach on an H.264 video decoder and an H.265 encoder targeting the latest Zynq-7000 platforms from Xilinx, embedding a Cortex-A9 dual-core processor. We show that an hardware/software implementation of the H.264 decoder using both processor cores and slice decomposition is possible under real-time constraints, effectively achieving a framerate of 30 frames per second while reducing area requirements compared to a static implementation, using 54 % less slice resources and 44 % less BRAM resources. Additionally we report the ability of the methodology to address very early analysis from high level application specification on the example of an H.265 encoder.

Mots clés: Real-time systems; Design space exploration; Reconfigurable architecture; Partial reconfiguration; Field programmable gate arrays

Domaines: Systèmes embarqués

François Duhem, Fabrice Muller, Robin Bonamy, Sebastien Bilavarn. FoRTReSS: a flow for design space exploration of partially reconfigurable systems. Design Automation for Embedded Systems, 2015, 19 (3), pp.301-326. ⟨10.1007/s10617-015-9160-2⟩. ⟨hal-01134008v2⟩