A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

Vianney Lapotre (1) , Purushotham Murugappa Velayuthan (2) , Guy Gogniat (1) , Amer Baghdadi (3, 2) , Michael Hübner (4) , Jean-Philippe Diguet (1)

1 Lab-STICC_UBS_CACS_MOCS
2 Lab-STICC_TB_CACS_IAS
3 ELEC - Département Electronique
4 RUB - Ruhr University Bochum = Ruhr-Universität Bochum

The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.

Mots clés: dynamic configuration; Application specific instruction-set processor (ASIP); turbo codes (TCs); wireless communication.; Wireless communication; turbo codes; ASIP; Dynamic configuration

Domaines: Electronique

Vianney Lapotre, Purushotham Murugappa Velayuthan, Guy Gogniat, Amer Baghdadi, Michael Hübner, et al.. A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24 (1), pp.383 - 387. ⟨10.1109/TVLSI.2015.2396941⟩. ⟨hal-01121754⟩