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A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

Abstract : A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the author's knowledge, this amplifier presents the highest figure of merit (FOM ITRS) among 60 GHz PAs using silicon technology.
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https://hal.archives-ouvertes.fr/hal-01110611
Contributor : Equipe Conception de Circuits <>
Submitted on : Wednesday, January 28, 2015 - 3:19:03 PM
Last modification on : Saturday, March 14, 2020 - 12:44:09 PM

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  • HAL Id : hal-01110611, version 1

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Aurélien Larie, Eric Kerherve, Baudouin Martineau, V. Knopik, Didier Belot. A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS. ESSCIRC 2014, Sep 2014, VENISE, Italy. pp.175-178. ⟨hal-01110611⟩

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