A Survey of Architectural Techniques For Improving Cache Power Efficiency

Sparsh Mittal (1)

1 ORNL - Oak Ridge National Laboratory [Oak Ridge]

Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-world processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling low-power operation of caches.

Mots clés: Cache energy saving techniques; architectural techniques; dynamic energy; leakage energy; power management; low-power; energy efficiency; green computing; classification; survey

Domaines: Architectures Matérielles [cs.AR]

Sparsh Mittal. A Survey of Architectural Techniques For Improving Cache Power Efficiency. Sustainable Computing : Informatics and Systems, 2014, 4 (1), pp.33-43. ⟨10.1016/j.suscom.2013.11.001⟩. ⟨hal-01103026⟩