An Axiomatic Memory Model for POWER Multiprocessors

Sela Mador-Haim (1) , Luc Maranget (2) , Susmit Sarkar (3) , Kayvan Memarian (3) , Jade Alglave (4) , Scott Owens (3) , Rajeev Alur (1) , Milo M, K. Martin (1) , Peter Sewell (3) , Derek Williams (5)

1 Department of Electrical and Systems Engineering
2 MOSCOVA - Mobililty, security, concurrence, verification and analysis
3 Computer Laboratory [Cambridge]
4 University of Oxford
5 IBM

The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and dis-allowed behaviors, posing challenges in specifying their memory models formally and accurately, and in understanding and analyzing the behav-ior of concurrent software. This complexity is particularly evident in the IBM R Power Architecture R , for which a faithful specification was pub-lished only in 2011 using an operational style. In this paper we present an equivalent axiomatic specification, which is more abstract and con-cise. Although not officially sanctioned by the vendor, our results indicate that this axiomatic specification provides a reasonable basis for reasoning about current IBM R POWER R multiprocessors. We establish the equiva-lence of the axiomatic and operational specifications using both manual proof and extensive testing. To demonstrate that the constraint-based style of axiomatic specification is more amenable to computer-aided ver-ification, we develop a SAT-based tool for evaluating possible outcomes of multi-threaded test programs, and we show that this tool is signifi-cantly more efficient than a tool based on an operational specification.

Domaines: Langage de programmation [cs.PL]; Calcul parallèle, distribué et partagé [cs.DC]

Sela Mador-Haim, Luc Maranget, Susmit Sarkar, Kayvan Memarian, Jade Alglave, et al.. An Axiomatic Memory Model for POWER Multiprocessors. Computer Aided Verification - 24th International Conference, CAV, ACM, Jul 2012, Berkely, United States. pp.495 - 512, ⟨10.1007/978-3-642-31424-7_36⟩. ⟨hal-01100773⟩