/. Input and . Output, SchedulingTable : scheduling table 1: for i := 1 to length(Path) do 2: ShiftSize := (i ? 1) * SegmentBufferSize, ShiftSize) 4: ShiftedIntervalList[i] := ShiftLeftIntervals(FreeIntervalList, p.=IntersectIntervals

S. Amarasinghe, M. I. Gordon, M. Karczmarek, J. Lin, D. Maze et al., Language and Compiler Design for Streaming Applications, International Journal of Parallel Programming, vol.19, issue.2, 2005.
DOI : 10.1007/s10766-005-3590-6

P. Aubry, P. Beaucamps, F. Blanc, B. Bodin, S. Carpov et al., Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor, Proceedings ALCHEMY 2013, 2013.
DOI : 10.1016/j.procs.2013.05.330

URL : https://hal.archives-ouvertes.fr/hal-00832504

I. Bacivarov, W. Haid, K. Huang, and L. Thiele, Methods and tools for mapping process networks onto multi-processor systems-on-chip, Handbook of Signal Processing Systems, 2013.

J. H. Bahn, J. Yang, and N. Bagherzadeh, Parallel FFT algorithms on network-on-chips, Proceedings ITNG 2008, 2008.

V. Bebelis, P. Fradet, A. Girault, and B. Lavigueur, A framework to schedule parametric dataflow applications on many-core platforms, Proceedings CPC'13, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00923670

T. Bjerregaard and J. Sparso, Implementation of guaranteed services in the MANGO clockless network-on-chip, IEE Proceedings - Computers and Digital Techniques, vol.153, issue.4, 2006.
DOI : 10.1049/ip-cdt:20050067

S. Borkar, Thousand core chips ? a technology perspective, Proceedings DAC, 2007.

E. Carara, N. Calazans, and F. Moraes, Router architecture for highperformance nocs, Proceedings SBCCI, 2007.

T. Carle and D. Potop-butucaru, Throughput Optimization by Software Pipelining of Conditional Reservation tables INRIA, Rapport de recherche RR-7606, ACM TACO. [Online]. Available, 2011.

T. Carle, D. Potop-butucaru, Y. Sorel, and D. Lesens, From dataflow specification to multiprocessor partitioned time-triggered realtime implementation, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00742908

R. Davis and A. Burns, A survey of hard real-time scheduling for multiprocessor systems, ACM Computing Surveys, vol.43, issue.4, 2011.
DOI : 10.1145/1978802.1978814

M. Djemal, F. Pêcheux, D. Potop-butucaru, R. De-simone, F. Wajsbürt et al., Programmable routers for efficient mapping of applications onto NoC-based MPSoCs, Proceedings DASIP, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00787497

P. Eles, A. Doboli, P. Pop, and Z. Peng, Scheduling with bus access optimization for distributed embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.8, issue.5, pp.472-491, 2000.
DOI : 10.1109/92.894152

G. Fohler and K. Ramamritham, Static scheduling of pipelined periodic tasks in distributed real-time systems, Proceedings Ninth Euromicro Workshop on Real Time Systems, pp.128-135, 1995.
DOI : 10.1109/EMWRTS.1997.613773

D. Genius, A. M. Kordon, and K. Z. Abidine, Space optimal solution for data reordering in streaming applications on NoC based MPSoC, Journal of Systems Architecture, vol.59, issue.7, 2013.
DOI : 10.1016/j.sysarc.2013.04.001

URL : https://hal.archives-ouvertes.fr/hal-01195936

M. Gerdes, F. Kluge, T. Ungerer, C. Rochange, and P. Sainrat, Time analysable synchronisation techniques for parallelised hard real-time applications, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012.
DOI : 10.1109/DATE.2012.6176555

J. Goossens, S. Funk, and S. Baruah, Priority-driven scheduling of periodic task systems on multiprocessors, Real-Time Systems, vol.25, issue.2-3, 2003.

K. Goossens, J. Dielissen, and A. Radulescu, AEthereal network on chip: Concepts, architectures, and implementations, IEEE Design & Test of Computers, vol.22, issue.5, 2005.

T. Grandpierre and Y. Sorel, From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings., 2003.
DOI : 10.1109/MEMCOD.2003.1210097

D. Hardy and I. Puaut, Wcet analysis of multi-level non-inclusive setassociative instruction caches, RTSS, 2008.

M. Harrand and Y. Durand, Network on chip with quality of service United States patent application publication US, 2011.

M. Herlihy and N. Shavit, The Art of Multiprocessor Programmin, 2008.

H. Kashif, S. Gholamian, R. Pellizzoni, H. Patel, and S. Fischmeister, ORTAP: An Offset-based response time analysis for a pipelined communication resource model, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013.
DOI : 10.1109/RTAS.2013.6531097

C. L. Layland, Scheduling algorithms for multiprogramming in a hard real-time environment, Journal of the ACM, vol.20, issue.1, 1973.

Z. Lu and A. Jantsch, Tdm virtual-circuit configuration for networkon-chip, IEEE Trans. VLSI, 2007.
DOI : 10.1109/tvlsi.2008.2000673

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.141.7401

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1269001

T. Moscibroda and O. Mutlu, A case for bufferless routing in on-chip networks, Proceedings ISCA-36, 2009.

L. Ni and P. Mckinley, A survey of wormhole routing techniques in direct networks, Computer, vol.26, issue.2, 1993.
DOI : 10.1109/2.191995

B. Nikolic, H. Ali, S. Petters, and L. Pinho, Are virtual channels the bottleneck of priority-aware wormhole-switched noc-based manycores, Proceedings RTNS, 2013, 2013.

I. M. Panades, A. Greiner, and A. Sheibanyrad, A low cost networkon-chip with guaranteed service well suited to the GALS approach, Proceedings NanoNet'06, 2006.

C. Pradalier, J. Hermosillo, C. Koike, C. Braillon, P. Bessì et al., The CyCab: a car-like robot navigating autonomously and safely among pedestrians, Robotics and Autonomous Systems, vol.50, issue.1, 2005.
DOI : 10.1016/j.robot.2004.10.002

URL : https://hal.archives-ouvertes.fr/inria-00182049

I. Puaut and D. Potop-butucaru, Integrated worst-case execution time estimation of multicore applications, Proceedings WCET'13, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00909330

A. Racu and L. Indrusiak, Using genetic algorithms to map hard realtime on noc-based systems, Proceedings ReCoSoC, 2012.

Z. Shi and A. Burns, Schedulability analysis and task mapping for real-time on-chip communication, Real-Time Systems, vol.6, issue.2, pp.360-385, 2010.
DOI : 10.1007/s11241-010-9108-3

R. Sorensen, M. Schoeberl, and J. Sparso, A light-weight statically scheduled network-on-chip, NORCHIP 2012, 2012.
DOI : 10.1109/NORCHP.2012.6403129

C. Villalpando, A. Johnson, R. Some, J. Oberlin, and S. Goldberg, Investigation of the Tilera processor for real time hazard detection and avoidance on the Altair Lunar Lander, 2010 IEEE Aerospace Conference, 2010.
DOI : 10.1109/AERO.2010.5447023

R. Wilhelm and J. Reineke, Embedded systems: Many cores — Many problems, 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), 2012.
DOI : 10.1109/SIES.2012.6356583

J. Xu, Multiprocessor scheduling of processes with release times, deadlines, precedence, and exclusion relations, IEEE Transactions on Software Engineering, vol.19, issue.2, pp.139-154, 1993.
DOI : 10.1109/32.214831

Y. Yoon, N. Concer, M. Petracca, and L. Carloni, Virtual channels vs. multiple physical networks, Proceedings of the 47th Design Automation Conference on, DAC '10, 2010.
DOI : 10.1145/1837274.1837315

J. T. Zhai, M. Bamakhrama, and T. Stefanov, Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems, Proceedings of the 50th Annual Design Automation Conference on, DAC '13, 2013.
DOI : 10.1145/2463209.2488944