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Article Dans Une Revue Analog Integrated Circuits and Signal Processing Année : 2015

Fully Integrated Doherty Power Amplifier in CMOS 65nm with Constant PAE in Backoff

Résumé

Design methodology and measurements re-sults are presented for a Doherty Power Amplier fullyintegrated with its input/output network matching andchoke inductances in 65 nm CMOS technology withconstant PAE over a 7 dB backo. Measurements from2.4 GHz to 2.6 GHz show constant PAE performancestarting in 20% level up to 24% with a maximum out-put power of 23.4 dBm. The circuit is fully describedwith all components values and layout details for fur-ther reproduction. Performance graphs showing the ac-tive load-pull eect, sub-ampliers behavior and con-stant PAE prove that it is a real Doherty Power Am-plier with all eects as known by the theory. The cir-cuit is composed by only lumped components, each sub-amplier has cascode topology and their input/outputnetworks are optimized to save die area and to producea constant PAE.
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Dates et versions

hal-01090492 , version 1 (03-12-2014)

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Marcos Carneiro, Eric Kerherve, Nathalie Deltimple, Didier Belot, Paulo H. P. de Carvalho. Fully Integrated Doherty Power Amplifier in CMOS 65nm with Constant PAE in Backoff. Analog Integrated Circuits and Signal Processing, 2015, Special Issue: Highlights From The Flagship Latin American Symposium On Circuits And Systems: Selected Papers From LASCAS 2013, 82 (issue 1), pp 89-97. ⟨10.1007/s10470-014-0451-5⟩. ⟨hal-01090492⟩
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