Using Controller-Synthesis Techniques to Build Property-Enforcing Layers, Proceedings of the 12th european conference on programming, pp.174-188, 2003. ,
DOI : 10.1007/3-540-36575-3_13
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.102.2186
The Sigali Tool Box Environment, 2006 8th International Workshop on Discrete Event Systems, pp.465-466, 2006. ,
DOI : 10.1109/WODES.2006.382518
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.81.5266
http://eurailmag.com/from-cable-to-chip-ferrocots-takes-commandcontrol/ ferrocots. Consulté sur http://eurailmag.com/from-cable-to-chip-ferrocots-takes -command-control, 2007. ,
25 years of model checking, pp.1-26, 2008. ,
Consulté sur http://dx.doi.org/10, p.1423536 ,
25 years of model checking Consulté sur http, pp.1-26, 2008. ,
Design, simulate & deploy automation & embedded control systems with higher efficiency. Consulté sur http, 2010. ,
A component-based safe design method for train control systems, Embedded real time software and systems erts, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-01091237
Safe design method of embedded control systems. Case study, Journal Europ??en des Syst??mes Automatis??s, vol.47, issue.4-8, 2013. ,
DOI : 10.3166/jesa.47.403-421
URL : https://hal.archives-ouvertes.fr/hal-00811615
What good is temporal logic Information processing, pp.657-668, 1983. ,
Using Formal Verification Techniques to Reduce Simulation and Test Effort, Proceedings of the international symposium of formal methods europe on formal methods for increasing software productivity, pp.465-477, 2001. ,
DOI : 10.1007/3-540-45251-6_27
octobre) Synthesis of Discrete- Event controllers based on the SignalEnvironment Consulté sur http, Discrete Event Dynamic Systems, vol.10, issue.4, pp.325-346, 2000. ,
DOI : 10.1023/A:1008311720696
Symbolic model checking: an approach to the state explosion problem, Thèse de doctorat non publiée, pp.92-24209, 1992. ,
The control of discrete event systems, Proceedings of the IEEE, vol.77, issue.1, pp.81-98, 1989. ,
DOI : 10.1109/5.21072
Specification Enforcing Refinement for Convertibility Verification, 2009 Ninth International Conference on Application of Concurrency to System Design, pp.148-15725, 2009. ,
DOI : 10.1109/ACSD.2009.25
URL : https://hal.archives-ouvertes.fr/hal-00753172