Parallel SHVC decoder: Implementation and analysis
Résumé
The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC decoder performs a real time decoding of 1600p60 video resolution.
Mots clés
code standards
computational complexity
image resolution
multiprocessing systems
parallel architectures
spatiotemporal phenomena
video coding
HEVC standard
Xeon processor
decoding complexity
decoding frame rate enhancement
decoding time reduction
frame-based parallelism
hybrid parallel processing approach
latency enhancement
latency reduction
multiloop coding structure
parallel SHVC decoder
parallel processing architecture
scalable high efficiency video coding
spatial SHVC frame decoding
temporal SHVC frame decoding
ultra high video resolution
wavefront parallel processing
Decoding
Encoding
Instruction sets
Memory management
Scalability
Standards
HEVC
SHVC
parallel processing
Domaines
Systèmes embarqués
Origine : Fichiers produits par l'(les) auteur(s)
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