Low data rate architecture for smart image sensor
Résumé
In this paper, we present an innovative smart image sensor architecture based on non-uniform sampling and event-driven asynchronous computing able to drastically decrease the image sensor data flow. The proposed low-power architecture has been designed in order to only extract the relevant image information from the image sensor. Therefore, we completely rethink the sensor architecture including the design of the analog and digital parts: pixel and digital read-out system respectively. However, the proposed architecture is able to drastically reduce the data stream by suppressing the spatial and temporal redundancies that exist in videos. Matlab and VHDL simulations were perform to validate the behavior of the pixel and of the read-out protocol. These simulation results meet our expectations and they validate the proposed ideas. In conclusion, this is a first proposition to reduce the power consumption of smart image sensors, especially in mobiles devices