Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing

Abstract : In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on the number of inter-FPGA signals to share the same physical wire and be time-multiplexed. In this paper, we propose an adaptation of Pathfinder routing algorithm that minimizes the verification time of multi-FPGA systems by reducing the multiplexing ratio per physical wire. To run real experiments, we propose a large benchmark generation environment and we show that the verification system clock frequency is improved by 17% on average compared with conventional methods
Document type :
Conference papers
Liste complète des métadonnées

https://hal.sorbonne-universite.fr/hal-01058039
Contributor : Mariem Turki <>
Submitted on : Tuesday, August 26, 2014 - 12:56:16 AM
Last modification on : Thursday, March 21, 2019 - 2:17:58 PM

Identifiers

Citation

Mariem Turki, Habib Mehrez, Zied Marrakchi. Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing. 2014 International Conference on Reconfigurable computing and FPGA, Dec 2012, Cancun, Mexico. 〈10.1109/ReConFig.2012.6416765〉. 〈hal-01058039〉

Share

Metrics

Record views

225