Distributed synchronous clocking, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.3, pp.314-328, 1995. ,
DOI : 10.1109/71.372779
Design and VHDL modeling of alldigital PLLs, 8 th IEEE international NEWCAS conf, pp.293-296, 2010. ,
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE Journal of Solid-State Circuits, vol.43, issue.1, 2008. ,
DOI : 10.1109/JSSC.2007.910966
A high-resolution flash timeto-digital converter and calibration, International Test Conference pp, pp.1148-1157, 2004. ,
Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks, Proceedings of the 2011 American Control Conference, pp.4691-4696, 2011. ,
DOI : 10.1109/ACC.2011.5991295
URL : https://hal.archives-ouvertes.fr/hal-01181176
Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, issue.4, pp.708-720, 2012. ,
DOI : 10.1109/TCSI.2011.2169745
URL : https://hal.archives-ouvertes.fr/hal-00695843
FPGA implementation of reconfigurable ADPLL network for distributed clock generation, 2011 International Conference on Field-Programmable Technology, pp.1-4, 2011. ,
DOI : 10.1109/FPT.2011.6132670
URL : https://hal.archives-ouvertes.fr/hal-01053755
Active GHz clock network using distributed PLLs, IEEE Journal of Solid-State Circuits, vol.35, issue.11, pp.1553-1560, 2000. ,
DOI : 10.1109/4.881199