Performance Improvement versus CPW and Loss Distribution Analysis of Slow-wave CPW in 65 nm HR-SOI CMOS Technology - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2013

Performance Improvement versus CPW and Loss Distribution Analysis of Slow-wave CPW in 65 nm HR-SOI CMOS Technology

Résumé

High-performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional coplanar waveguides (CPW) fabricated in a 65-nm High-Resistivity-SOI (HR-SOI) CMOS technology. As expected, S-CPW demonstrates better performance at millimeter-wave frequencies in term of higher effective dielectric permittivity, which is due to the patterned floating shield inserted between the transmission line and the substrate. In addition, S-CPW shows a lower attenuation constant despite of the added metallic patterned floating shield on HR substrate. For demonstration purpose, both low- and high- characteristic impedance S-CPW and CPW are characterized. For 28-Ω S-CPW and 65-Ω S-CPW, the effective dielectric permittivity is improved by a factor of 6 and 2, respectively. Meanwhile, attenuation constants of slow-wave structures are lower than 0.9 dB/mm and 0.57 dB/mm at 60 GHz, compared to CPW ones which are as high as 1.5 dB/mm and 0.95 dB/mm, respectively. Furthermore, the loss distribution for the S-CPW structure is detailed by varying the patterned floating shield length for both standard Bulk and HR-SOI substrates.
Fichier non déposé

Dates et versions

hal-01025022 , version 1 (17-07-2014)

Identifiants

Citer

Xiaolan Tang, Anne-Laure Franc, Emmanuel Pistono, A. Siligaris, P. Vincent, et al.. Performance Improvement versus CPW and Loss Distribution Analysis of Slow-wave CPW in 65 nm HR-SOI CMOS Technology. IEEE Transactions on Electron Devices, 2013, 59 (5), pp.1279-1285. ⟨10.1109/TED.2012.2186969⟩. ⟨hal-01025022⟩
208 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More