Output parameter reduction for an efficient evaluation of alternative test techniques

Abstract : Lengthy test times and highly sophisticated test equipment are the main reasons of the high costs of analog/RF specification based testing. Alternative test measures, extracted by means of built in test techniques, are a promising approach to replace standard specification based tests. The quality of these test measures must be evaluated at the design stage, before the actual production, in order to select the most appropriate ones. The estimation of test metrics is complicated by the multidimensional nature of the problem, including multiple circuit performances that a device under test must verify in order to comply with the specifications, and multiple alternative test measures that are proposed as lower cost replacements. In this paper, we present a technique to reduce the number of circuit performances and test measures (jointly called output parameters) for the estimation of test metrics. To validate the proposed approach, an RF LNA is considered. This circuit has three performances that must be verified by a functional device and two alternative test measures that are proposed to replace the circuit performances. With the use of the proposed approach, we will show that only one circuit performance and one alternative test measure need to be considered for an accurate estimation of the parametric test escapes and yield loss of the alternative test technique
Keywords : test parametric-tests
Type de document :
Communication dans un congrès
28th International Conference on Design of Circuits and Integrated Systems (DCIS'13), San Sebastian, Spain, Nov 2013, San Sebastian, Spain. 2013, Proceedings
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https://hal.archives-ouvertes.fr/hal-01017501
Contributeur : Lucie Torella <>
Soumis le : mercredi 2 juillet 2014 - 16:07:28
Dernière modification le : mardi 16 janvier 2018 - 15:54:23

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  • HAL Id : hal-01017501, version 1

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K. Beznia, A. Bounceur, Salvador Mir, R. Euler. Output parameter reduction for an efficient evaluation of alternative test techniques. 28th International Conference on Design of Circuits and Integrated Systems (DCIS'13), San Sebastian, Spain, Nov 2013, San Sebastian, Spain. 2013, Proceedings. 〈hal-01017501〉

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