Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

S. Ghosh (1) , B. Grandchamp (2) , G. A. Koné (1) , F. Marc (1) , C. Maneux (1) , T. Zimmer (1) , V. Nodjiadjim (3) , M. Riet (3) , J. Y. Dupuy , J. Godin (3)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 OMMIC
3 III-V Lab - Alcatel-Thalès III-V lab

Domaines: Micro et nanotechnologies/Microélectronique

S. Ghosh, B. Grandchamp, G. A. Koné, F. Marc, C. Maneux, et al.. Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design. 22th European Symposium on the RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS, Oct 2011, bordeaux, France. pp.1-4. ⟨hal-01002192⟩