Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

M. Dimopulos (1) , Yi Gang (1) , Mounir Benabdenbi (1) , Lorena Anghel (1) , Nacer-Eddine Zergainoh (1) , M. Nicolaidis (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

Mots clés: failure analysis; fault tolerant computing; network-on-chip

Domaines: Micro et nanotechnologies/Microélectronique

M. Dimopulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, et al.. Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, France. pp.7-12, ⟨10.1109/IOLTS.2013.6604043⟩. ⟨hal-00997169⟩