A Flexible NISC-Based LDPC Decoder
Résumé
Low density parity-check (LDPC) codes, are widely used for error correction in digital communication systems. Their inclusion in communication standards requires to define decoders able to support efficiently a set of codes with different code length, code rates or code structures. In addition to this high flexibility, these decoders still have to achieve high throughputs in order to comply with standards requirements. In this paper, we propose to address the problem of designing generic and efficient LDPC decoders by using a nonsymmetric NISC-based architecture that performs layered decoding. NISC architectures provide flexibility with a limited loss in hardware efficiency. In addition, an automated design flow is used to efficiently assign computations to the processing units (PU) and to map data to the memory units (MU). Unlike previous works, the NISC decoder can include a number of PUs that is different than the number of MUs. This nonsymmetric characteristic provides a higher degree of freedom during the computation/data assignment phase of the design flow. This whole design framework automatically generates an LDPC decoder able to support any set of predetermined LDPC codes regardless of their parameters. The automated nature of the design framework enables to easily explore the design space for a given set of codes. Compared to state of the art LDPC decoders, the automatically generated decoders achieve higher hardware efficiency even for the challenging-to-implement unstructured LDPC codes.