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Communication Dans Un Congrès Année : 2014

Fully Integrated CMOS Doherty Power Amplifier with Network Matching Optimization for Die Size Reduction

Résumé

Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, Pout of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the Pout in 2dB
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Dates et versions

hal-00984573 , version 1 (28-04-2014)

Identifiants

  • HAL Id : hal-00984573 , version 1

Citer

Marcos Carneiro, Nathalie Deltimple, Paulo H. P. de Carvalho, Didier Belot, Eric Kerherve. Fully Integrated CMOS Doherty Power Amplifier with Network Matching Optimization for Die Size Reduction. European Microwave Conference 2014, Oct 2014, Rome, Italy. pp.1-4. ⟨hal-00984573⟩
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