Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

Abstract : A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad. The active area of the circuit is about 0.04 mm2.
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Journal articles
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https://hal.archives-ouvertes.fr/hal-00983408
Contributor : Equipe Conception de Circuits <>
Submitted on : Friday, April 25, 2014 - 11:35:11 AM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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  • HAL Id : hal-00983408, version 1

Citation

Yohan Piccin, H. Lapuyade, Yann Deval, Colette Morche, J. -Y. Seyler, et al.. Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, pp.25-30. ⟨hal-00983408⟩

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