Skip to Main content Skip to Navigation
Poster communications

Towards high performance GHASH for pipelined AES-GCM using FPGAs

Abstract : AES-GCM has been utilized in various security applications. It consists of two components: an Advanced Encryption Standard (AES) engine and a Galois Hash (GHASH) core. The performance of the system is determined by the GHASH architecture because of the inherent computation feedback. This paper introduces a modification for the pipelined Karatsuba Ofman Algorithm (KOA)-based GHASH. In particular, the computation feedback is removed by analyzing the complexity of the computation process. The proposed GHASH core is evaluated with three different implementations of AES ( BRAMs-based SubBytes, composite field-based SubBytes, and LUT-based SubBytes). The presented AES-GCM architectures are implemented using Xilinx Virtex5 FPGAs. Our comparison to previous work reveals that our architectures are more performance-efficient (Thr. /Slices).
Document type :
Poster communications
Complete list of metadatas
Contributor : Qingshan Tang <>
Submitted on : Wednesday, April 2, 2014 - 12:08:52 PM
Last modification on : Thursday, March 21, 2019 - 2:30:33 PM



Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang. Towards high performance GHASH for pipelined AES-GCM using FPGAs. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. ACM, pp.242-242, 2014, ⟨10.1145/2554688.2554709⟩. ⟨hal-00969267⟩



Record views