Metrology and Linewidth roughness issues during complex metal/high-k gate stack patterning for sub-20nm technological nodes

E. Pargon (1) , M. Fouchier (1) , M. Brihoum (1) , L. Azarnouche , K. Menguelti , J. Jussot (1) , O. Ros (1) , B. Icard (2) , P. Gouraud (3)

1 LTM - Laboratoire des technologies de la microélectronique
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 ST-CROLLES - STMicroelectronics [Crolles]

E. Pargon, M. Fouchier, M. Brihoum, L. Azarnouche, K. Menguelti, et al.. Metrology and Linewidth roughness issues during complex metal/high-k gate stack patterning for sub-20nm technological nodes. 60th International AVS Symposium & Topical Conferences, Oct 2013, Long Beach, United States. ⟨hal-00951022⟩