Numerical Reproducibility for the Parallel Reduction on Multi- and Many-Core Architectures

Abstract : On modern multi-core, many-core, and heterogeneous architectures, floating-point computations, especially reductions, may become non-deterministic and, therefore, non-reproducible mainly due to the non-associativity of floating-point operations. We introduce an approach to compute the correctly rounded sums of large floating-point vectors accurately and efficiently, achieving deterministic results by construction. Our multi-level algorithm consists of two main stages: a filtering stage that relies on fast vectorized floating-point expansions, and an accumulation stage based on superaccumulators in a high-radix carry-save representation. We present implementations on recent Intel desktop and server processors, Intel Xeon Phi accelerators, and both AMD and NVIDIA GPUs. We show that numerical reproducibility and bit-perfect accuracy can be achieved at no additional cost for large sums that have dynamic ranges of up to 90 orders of magnitude by leveraging arithmetic units that are left underused by standard reduction algorithms.
Type de document :
Pré-publication, Document de travail
2015
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https://hal.archives-ouvertes.fr/hal-00949355
Contributeur : Roman Iakymchuk <>
Soumis le : jeudi 10 septembre 2015 - 15:49:43
Dernière modification le : mercredi 2 août 2017 - 10:10:32
Document(s) archivé(s) le : mardi 29 décembre 2015 - 00:05:21

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superaccumulator.pdf
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  • HAL Id : hal-00949355, version 4

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Sylvain Collange, David Defour, Stef Graillat, Roman Iakymchuk. Numerical Reproducibility for the Parallel Reduction on Multi- and Many-Core Architectures. 2015. <hal-00949355v4>

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