A compiled Cycle Accurate Simulation for Hardware Architecture

Adrien Bullich (1) , Mikaël Briday (1) , Jean-Luc Béchennec (1) , Yvon Trinquet (2)

1 Systèmes Temps Réel
2 IRCCyN - Institut de Recherche en Communications et en Cybernétique de Nantes

The context of our research works is the real-time embedded systems domain. It is often difficult to test systems in order to ensure an appropriate running. A simulator presents the advantage that the detailed evolution of each component can be followed. These simulators require a very long development time. HARMLESS has been developed to automate this step. It is a hardware description language (HADL), readable by a compiler which allows the generation of a functional simulator (ISS) and a temporal simulator (CAS). CAS are costful in execution time. Several techniques exist in the literature to improve the speed of temporal simulators. In this paper we explore a new approach: the compiled simulation, which is used for functional simulators.

Domaines: Systèmes embarqués

Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet. A compiled Cycle Accurate Simulation for Hardware Architecture. 5th International Conference on Advances in System Simulation - SIMUL 2013, Oct 2013, VENICE, Italy. pp.213-225. ⟨hal-00943401⟩