Event-clock Message Passing Automata: A logical characterization and an emptiness checking algorithm

Sundararaman Akshay (1) , Benedikt Bollig (2, 3) , Paul Gastin (2, 3)

1 Department of Computer Science and Engineering [Bombay]
2 LSV - Laboratoire Spécification et Vérification [Cachan]
3 MEXICO - Modeling and Exploitation of Interaction and Concurrency

Domaines: Théorie et langage formel [cs.FL]

Sundararaman Akshay, Benedikt Bollig, Paul Gastin. Event-clock Message Passing Automata: A logical characterization and an emptiness checking algorithm. Formal Methods in System Design, 2013, 42 (3), pp.262-300. ⟨hal-00925745⟩