Skip to Main content Skip to Navigation
Conference papers

Redundancy Method to assess Electromigration Lifetime in power grid design

Abstract : The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.
Document type :
Conference papers
Complete list of metadata

Cited literature [7 references]  Display  Hide  Download
Contributor : Boukary Ouattara <>
Submitted on : Thursday, December 12, 2013 - 10:53:57 AM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Thursday, March 13, 2014 - 12:00:21 AM


Files produced by the author(s)



Boukary Ouattara, Lise Doyen, David Ney, Habib Mehrez, Pirouz Bazargan-Sabet, et al.. Redundancy Method to assess Electromigration Lifetime in power grid design. IEEE International Interconnect Technology Conference (IITC),, Jun 2013, Kyoto, Japan. pp.81-83, ⟨10.1109/IITC.2013.6615570⟩. ⟨hal-00915971⟩



Record views


Files downloads