Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization
Résumé
The variety of wireless communication standards and their corresponding applications requires more and more flexible, yet efficient, implementations. The emerging flexibility need induces a new challenge when added to the ever increasing requirements in terms of high throughput and low complexity. This paper presents a design of an application-specific processor dedicated for a minimum mean square error interference cancellation (MMSE-IC) linear equalizer (LE) used in iterative multi-input multi-output (MIMO) turbo receiver. The explored design approach applies static scheduling of datapath control signals. The proposed architecture supports the requirements of flexibility for different MIMO system configurations concerning channel time selectivity and transmission diversity. In order to evaluate the efficiency of the adopted architecture model for this kind of applications and requirements, a fair comparison is conducted with a state-of-the-art application specific instruction-set processor (ASIP) implementation. The obtained results illustrate a significant performance improvement in terms of execution time and implementation area while using identical computational resources and supporting same flexibility parameters.