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Physical Design Exploration of 3D Tree-based FPGA Architecture

Abstract : An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to distribute the Tree-based interconnect netwrok into multiple stacked active silicon layers proposed in this paper.
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Contributor : Vinod Pangracious <>
Submitted on : Tuesday, October 15, 2013 - 2:47:56 PM
Last modification on : Thursday, March 21, 2019 - 2:32:17 PM
Document(s) archivé(s) le : Friday, April 7, 2017 - 11:10:42 AM


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Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi. Physical Design Exploration of 3D Tree-based FPGA Architecture. GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, May 2013, Paris, France. pp.335-336, ⟨10.1145/2483028.2483130⟩. ⟨hal-00873292⟩



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