A. Dehon, Reconfigurable Architectures for General-Purpose Computing, 1996.

A. Rahman and R. Reif, System-level performance evaluation of three-dimensional integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.8, issue.6, 2000.
DOI : 10.1109/92.902261

D. Kim, S. Mukhopadhyay, and . Lim, Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs, Proceedings of the 11th international workshop on System level interconnect prediction, SLIP '09, pp.85-92, 2009.
DOI : 10.1145/1572471.1572486

V. Pangracious, . Marrakchi, H. Amouri, and . Meherez, Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA, 2013.
DOI : 10.1007/978-3-642-36812-7_19

URL : https://hal.archives-ouvertes.fr/hal-00872757

Z. Marrakchi, . Mrabet, H. Farooq, and . Mehrez, FPGA Interconnect Topologies Exploration, International Journal of Reconfigurable Computing, vol.12, issue.10, 2009.
DOI : 10.1109/4.62145

URL : https://hal.archives-ouvertes.fr/hal-01197287

K. Siozios, D. Bartzas, and . Soudris, Architecture Level Exploration of Alternative schmes Targeting 3D FPGAs: A Software Supported Methodology, International Journal of Reconfigurable Computing, 2008.

C. Ababei, Y. Feng, and . Goplen, Placement and Routing in 3D Integrated Circuits, IEEE Design and Test of Computers, vol.22, issue.6, p.520531, 2005.
DOI : 10.1109/MDT.2005.150

S. Velusamy, Monitoring temperature in FPGA based SoCs, 2005 International Conference on Computer Design, 2005.
DOI : 10.1109/ICCD.2005.78

J. Ayala, . Sridhar, . Pangracious, Y. Atienza, and . Leblebici, Through Silicon Via-Based Grid for Thermal Control in 3D Chips NanoNet pp, pp.90-98, 2009.

D. Jang, C. Ryu, and K. Lee, Development and evaluation of 3-D SiP with vertically interconnected Through Silicon Vias (TSV) Proceedings of the 57th ECTC '07, pp.847-852, 2007.