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Performance analysis and optimization of high density tree-based 3d multilevel FPGA

Vinod Pangracious 1, * Zied Marrakchi 2 Emna Amouri 1 Habib Mehrez 1
* Corresponding author
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments.
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Contributor : Vinod Pangracious <>
Submitted on : Tuesday, October 15, 2013 - 9:10:58 AM
Last modification on : Thursday, March 21, 2019 - 2:33:03 PM
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Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez. Performance analysis and optimization of high density tree-based 3d multilevel FPGA. Reconfigurable Computing: Architectures, Tools and Applications, Mar 2013, Los Angeles, CA, United States. pp.197-209, ⟨10.1007/978-3-642-36812-7_19⟩. ⟨hal-00872757⟩



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