Self-Adaptive Network-on-Chip Interface

Rachid Dafali (1) , Jean-Philippe Diguet (1) , J.-C. Créput (1, 2)

1 Lab-STICC_UBS_CACS_MOCS
2 SET - Laboratoire Systèmes et Transports

This paper presents an original approach of bandwidth-oriented self-adaptivity in the domain of Network-on-Chip, where reconfiguration is handled by network interfaces offering traffic with guarantee of service. Reconfiguration is first based on multiple FIFOs with variables bounds and implemented in a single dual-port memory with a dedicated controller. Secondly, it relies on multiple and compliant TDMA tables based on a new heuristic for path computation. Combination of both techniques provide significant bandwidth improvement with a negligible resource overhead. The proposed solution is demonstrated with cycle-accurate VHDL simulation and FPGA implementation for synthetic and image processing applications.

Mots clés: dynamic reconfiguration; Reconfigurable Network-on-Chip; self-adaptivity; FIFO; TDMA; network-interfaces

Domaines: Architectures Matérielles [cs.AR]

Rachid Dafali, Jean-Philippe Diguet, J.-C. Créput. Self-Adaptive Network-on-Chip Interface. IEEE Embedded Systems Letters, 2013, 5 (4), ⟨10.1109/LES.2013.2285175⟩. ⟨hal-00871866⟩