Pre- and post-scheduling memory allocation strategies on MPSoCs

Karol Desnos 1, 2 Maxime Pelcat 1 Jean François Nezan 1 Slaheddine Aridhi 3
1 IETR - Institut d'Electronique et de Télécommunications de Rennes
2 UEB - Université européenne de Bretagne - European University of Brittany
3 CIV Texas Instruments
Abstract : This paper introduces and assesses a new method to allocate memory for applications implemented on a shared memory Multiprocessor System-on-Chip (MPSoC). This method first consists of deriving, from a Synchronous Dataflow (SDF) algorithm description, a Memory Exclusion Graph (MEG) that models all the memory objects of the application and their allocation constraints. Based on the MEG, memory allocation can be performed at three different stages of the implementation process: prior to the scheduling process, after an untimed multicore schedule is decided, or after a timed multicore schedule is decided. Each of these three alternatives offers a distinct trade-off between the amount of allocated memory and the flexibility of the application multicore execution. Tested use cases are based on descriptions of real applications and a set of random SDF graphs generated with the SDF For Free (SDF3) tool. Experimental results compare several allocation heuristics at the three implementation stages. They show that allocating memory after an untimed schedule of the application has been decided offers a reduced memory footprint as well as a flexible multicore execution.
Keywords : data flow graphs multiprocessing systems scheduling storage allocation system-on-chip
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Karol Desnos, Maxime Pelcat, Jean François Nezan, Slaheddine Aridhi. Pre- and post-scheduling memory allocation strategies on MPSoCs. Electronic System Level Synthesis Conference (ESLSyn13), May 2013, Austin, TX, United States. pp.60-65. ⟨hal-00868945⟩

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