Effect of die metallization layer ageing in the case of power semiconductor devices

Sylvie Pommier (1) , Stéphane Lefebvre (2) , Sylvain Pietranico (3) , Mounira Berkani (2) , Zoubir Khatir (4) , Serge Bontemps (5) , Emmanuel Cadel (6)

1 LMT - Laboratoire de Mécanique et Technologie
2 SATIE - Systèmes et Applications des Technologies de l'Information et de l'Energie
3 ENS Cachan - École normale supérieure - Cachan
4 IFSTTAR/LTN - Laboratoire des Technologies Nouvelles
5 Microsemi, Power Module Products SAS
6 GPM - Groupe de physique des matériaux

The paper describes ageing mechanisms of the metallization layer deposited on the chips of power semiconductor devices, and the effects of its ageing on the electrical characteristics of a COOLMOSTM Transistor. We have tried to link the changes in electrical performances to the metallization degradation, in order to better understand the origin of the physical mechanisms of ageing and the effects of the degradation of the metallization layer on electrical performances of tested devices.

Mots clés: FIABILITE; SEMICONDUCTEUR; VIEILLISSEMENT

Domaines: Electronique

Sylvie Pommier, Stéphane Lefebvre, Sylvain Pietranico, Mounira Berkani, Zoubir Khatir, et al.. Effect of die metallization layer ageing in the case of power semiconductor devices. European Journal of Electrical Engineering, 2011, 14 (5), pp.569-585. ⟨10.3166/Geo.19.11-38⟩. ⟨hal-00861667⟩