Flexible, extensible, open-source and affordable FPGA-based traffic generator

Tristan Groleat 1, 2 Matthieu Arzel 3, 4 Sandrine Vaton 1, 2 Alban Bourge 5 Yannick Le Balch 5 Hicham Bougdal 5
2 REOP - Réseaux d'opérateurs
IRISA-D2 - RÉSEAUX, TÉLÉCOMMUNICATION ET SERVICES, Télécom Bretagne
4 Lab-STICC_TB_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : As high-speed links become ubiquitous in current networks, testing new algorithms at high-speed is essential for researchers. This task often requires traffic to be generated with some specied features : distribution of packet sizes, payload content, number of TCP or UDP ows... When targeting a data rate of many Gb/s, this cannot be done with commodity computers. Commercial traffic generators exist for this task, but they are expensive and do not t the precise needs of researchers. In this paper, we describe an open-source implementation of a traffic generator capable of lling a 10 Gb/s Ethernet link, with traffic features specied in software. The implementation works on a board including an FPGA and a 10 Gb/s network interface, like the Combo from INVEA-TECH or the NetFPGA 10G. These boards are a ordable for research and can provide a congurable and easily extensible traffic generator.
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Submitted on : Tuesday, October 1, 2013 - 11:59:36 AM
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Tristan Groleat, Matthieu Arzel, Sandrine Vaton, Alban Bourge, Yannick Le Balch, et al.. Flexible, extensible, open-source and affordable FPGA-based traffic generator. HPDC 2013 : 22nd International ACM Symposium on High Performance Parallel and Distributed Computing, Jun 2013, New-York, United States. ⟨hal-00859291⟩

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