An efficient BER-Based Reliability Method For SRAM-based FPGA

Fouad Sahraoui (1) , Fakhreddine Ghaffari (1) , Mohamed El Amine Benkhelifa (1) , Bertrand Granado (2)

1 ASTRE [Cergy-Pontoise]
2 SYEL - Systèmes Electroniques

Single Event Upset (SEU) is a major concern for SRAM-based FPGAs where a simple bit-flip can lead to an abnormal execution. We present in this paper, a new fault tolerance method based on hardware BER (Backward Error Recovery) to protect/correct system against the occurrence of transient faults. We use the partial dynamic reconfiguration offered by Xilinx Virtex-5 FPGAs to ensure hardware checkpoint and upon detection of fault we use recovery. Our method has several advantages: first it is non-intrusive (no internal modification of hardware modules of the system), second it is not based on redundant hardware resources (like most methods in the literature), and finally it has a static area overhead ratio when applied to a system. To validate our approach, we implemented it on a Xilinx platform based on a Partial Reconfigurable Region (PRR).

Mots clés: Fault tolerance; Checkpoint; Recovery; SRAM-based FPGAs; partial dynamic reconfiguration; readback

Domaines: Systèmes embarqués

Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado. An efficient BER-Based Reliability Method For SRAM-based FPGA. 7th IEEE International Design and Test Symposium IDT'2012, Dec 2012, Doha, Qatar. 6 p. ⟨hal-00854818⟩