From Formal Specifications to Efficient Test Scenarios Generation
Résumé
Various formal testing methods have been developed in the past decades. Most of them are based on graphical notations such as finite state machines, labelled transitions systems, etc., which remain quite intuitive for users to perform black box testing. In addition, testing methods based on temporal logics have been also investigated, such as the testing methods inspired by model checking. However, testing with model checkers often needs a model of System Under Test (SUT) to be known. This paper discusses a method for generating test cases from specifications expressed in CTL temporal logic, under a black-box framework. The test generation process from CTL is inspired by Banerjee et al.'s work which has developed a technique to generate non-vacuous test scenarios from LTL properties. The essential step of our test generation method is to rewrite a pertinent CTL property in terms of present state Boolean propositions and X(Next)-guarded temporal properties. The generated test benches are implemented within the ControlBuild tool.