Fully Integrated Doherty Power Amplifier Electromagnetically Optimized in CMOS 65nm with Constant PAE in Backoff

Marcos Carneiro (1, 2) , Nathalie Deltimple (1) , Didier Belot (3) , P.H.P. Carvalho (2) , Eric Kerhervé (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 UnB - Universidade de Brasilia [Brasília]
3 STMicroelectronics

A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. Electromagnetic models of each layout path were included in the optimization to dimension circuit components regarding parasitics of an accurate model. The method increased the PAE level in 6% through a constant 8.75 dB backoff range and increased in 2 dB the output power. The amplifier has an output power of 24 dBm, the first PAE peak is 26% and the second one 27%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce the number of inductances and to correctly balance active-loadpull effect. Comparisons were done between schematic, post-layout and electromagnetic simulation.

Domaines: Electronique

Marcos Carneiro, Nathalie Deltimple, Didier Belot, P.H.P. Carvalho, Eric Kerhervé. Fully Integrated Doherty Power Amplifier Electromagnetically Optimized in CMOS 65nm with Constant PAE in Backoff. NEWCAS 2013, Jun 2013, PARIS, France. pp.1-4. ⟨hal-00842195⟩