VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs
Résumé
In this work, we expose our approach to design and optimize mixed analogue and digital systems at a high level description using the hardware description language VHDL-AMS. Many statistical experimental design methods are employed in optimization. We apply Hocke_D4 experimental designs with five parameters in order to minimize the lock time and the spurious level of a fractional-N synthesizer acting as a direct MSK modulator and designed for the DECT standard application.