M. Anis and M. H. Aburahma, Leakage Current Variability in Nanometer Technologies'', 9th IDEA Symposium, pp.60-63, 2005.

R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, Statistical estimation of leakage current considering inter- and intra-die process variation, Proceedings of the 2003 international symposium on Low power electronics and design , ISLPED '03, pp.84-89, 2003.
DOI : 10.1145/871506.871530

S. Mukhopadhyay and K. Roy, Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation, Proc. of the international Symposium on Low Power Electronics and Design, pp.172-175, 2003.

T. Li, W. Zhang, and Z. Yu, Full-chip leakage analysis in nano-scale technologies, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.594-599, 2008.
DOI : 10.1145/1391469.1391622

Z. Hao, R. Shen, S. X. Tan, -. , B. Liu-;-guoyong et al., Statistical full-chip dynamic power estimation considering spatial correlations, 2011 12th International Symposium on Quality Electronic Design, pp.1-6, 2011.
DOI : 10.1109/ISQED.2011.5770802

R. Khaled, S. Heloue, . Member, N. Ieee, F. N. Azizi et al., Full-Chip Model for Leakage Current Estimation Considering Within-Die Correlation'', Computer Aided Design of Integrated Circuits and Systems, IEEE Transactions, pp.874-887, 2009.

C. D. Agostino, P. Flatresse, E. Beigne, and M. Belleville, An Accurate Approach for Statistical Estimation of Leakage Current Considering Multi-Parameter Process Variations in Nanometer CMOS Technologies, Proc. of ESSDERC, 2009.

A. Ferre, Leakage power bounds in CMOS digital technologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21, issue.6, pp.731-738, 2002.
DOI : 10.1109/TCAD.2002.1004317

J. Viraraghavan, Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization, 21st International Conference on VLSI Design (VLSID 2008), pp.667-672, 2008.
DOI : 10.1109/VLSI.2008.38

D. Helms, Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation, Proceedings of the 2006 international symposium on Low power electronics and design , ISLPED '06, pp.220-225, 2006.
DOI : 10.1145/1165573.1165628

H. Chang and S. S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.523-528, 2005.
DOI : 10.1145/1065579.1065716

A. Agarwal, K. Kang, and K. Roy, Accurate estimation and modeling of total chip leakage considering inter- & amp; intra-die process variations, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp.736-741, 2005.
DOI : 10.1109/ICCAD.2005.1560162

H. Chang and S. S. Sapatnekar, Statistical timing analysis considering spatial correlations using a single PERT-like traversal, ICCAD, pp.621-625, 2003.