P. Manet, An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications, EURASIP Journal on Embedded Systems, vol.2005, issue.55, 2008.
DOI : 10.1109/JSSC.2007.909344

S. Taha, A. Radermacher, S. Gérard, and J. Dekeyser, MARTE: UML-based Hardware Design from Modelling to Simulation, 2007.

. Standard and . Ip-xact, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows, IEEE Std, 1685.

J. Vidal, F. De-lamotte, G. Gogniat, J. Diguet, and P. Soulard, IP reuse in an MDA MPSoPC co-design approach, 2009 International Conference on Microelectronics, ICM, pp.256-259, 2009.
DOI : 10.1109/ICM.2009.5418638
URL : https://hal.archives-ouvertes.fr/hal-00454761

I. R. Quadri, S. Meftali, and J. Dekeyser, Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.68-75, 2010.
DOI : 10.1109/DASIP.2010.5706248
URL : https://hal.archives-ouvertes.fr/inria-00525003

W. Kruijtzer, Industrial IP integration flows based on IP-XACT standards, 2008 Design, Automation and Test in Europe, pp.32-37, 2008.
DOI : 10.1109/DATE.2008.4484656

C. Lennard, Industrially Proving the SPIRIT Consortium Specifications for Design Chain Integration, DATE'06, pp.1-6, 2006.

F. , H. , and E. Villar, A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation Specification and Design Languages (FDL), Forum on, pp.1-8, 2011.

E. G. Ochoa-ruiz, H. Bourennane, O. Rabah, and . Labbani, High-Level Modeling and Automatic Generation of Dynamically Reconfigurable Systems, Proceedings of the DASIP Conference, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00674299

O. G. Ochoa-ruiz, E. B. Labbani, P. Bourennane, and . Soulard, Model-Driven approach for automatic dynamic partially reconfigurable ip customization, RAW 2012, Sodius Corporation, MDWorkbench, 2011.