Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

Abstract : This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the generated IP-XACT through model transformations. We detail how certain IP-XACT objects are exploited in our approach; the emphasis is given to the generation of IP cores in a Xilinx EDK environment. We provide a case study in which a complete DPR platform is modeled in MARTE and implemented in a FPGA.
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Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, et al.. Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), Oct 2012, Finland. pp.107 -113. ⟨hal-00788463⟩

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