V. Variable and . Type, Variable ?: list mem

|. Einput, Input t) ? expr t | Eread_r : ? t, member ? (Reg t) ? expr t | Eread_rf : ? n t, member ? (Regfile n t) ? V

N. Benton, C. Hur, A. Kennedy, and C. Mcbride, Strongly Typed Term Representations in Coq, Journal of Automated Reasoning, vol.14, issue.1, pp.141-159, 2012.
DOI : 10.1007/s10817-011-9219-0

G. Berry, The foundations of Esterel, Proof, Language, and Interaction, Essays in Honour of Robin Milner, 2000.

S. Beyer, C. Jacobi, D. Kröning, D. Leinenbach, and W. J. Paul, Putting it all together ??? Formal verification of the VAMP, International Journal on Software Tools for Technology Transfer, vol.20, issue.2, pp.4-5411, 2006.
DOI : 10.1007/s10009-006-0204-6

P. Bjesse, K. Claessen, M. Sheeran, and S. Singh, Lava: Hardware Design in Haskell, Proc. ICFP, pp.174-184, 1998.

A. Bove and T. Coquand, Formalising Bitonic Sort in Type Theory, Proc. TYPES, pp.82-97, 2006.
DOI : 10.1007/11617990_6

A. Chlipala, Parametric higher-order abstract syntax for mechanized semantics, Proc. ICFP, pp.143-156, 2008.

A. Chlipala, A verified compiler for an impure functional language, Proc. POPL, pp.93-106, 2010.

K. Claessen, M. Sheeran, and S. Singh, The Design and Verification of a Sorter Core, Proc. CHARME, pp.355-369, 2001.
DOI : 10.1007/3-540-44798-9_28

T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2001.

S. Coupet-grimal and L. Jakubiec, Certifying circuits in type theory. Formal Asp, Comput, vol.16, issue.4, pp.352-373, 2004.

N. Dave, A. , and M. Pellauer, Scheduling as Rule Composition, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007), pp.51-60, 2007.
DOI : 10.1109/MEMCOD.2007.371249

M. Gordon, Why Higher-Order Logic is a Good Formalism for Specifying and Verifying Hardware, 1985.

M. J. Gordon, Relating Event and Trace Semantics of Hardware Description Languages, The Computer Journal, vol.45, issue.1, pp.27-36, 2002.
DOI : 10.1093/comjnl/45.1.27

F. K. Hanna, N. Daeche, and M. Longley, Veritas+: A specification language based on type theory, Hardware Specification, Verification and Synthesis, pp.358-379, 1989.
DOI : 10.1007/0-387-97226-9_37

W. A. Hunt-jr and B. Brock, The Verification of a Bit-slice ALU. In Hardware Specification, Verification and Synthesis, LNCS, vol.408, pp.282-306, 1989.

X. Leroy, A Formally Verified Compiler Back-end, Journal of Automated Reasoning, vol.27, issue.1, pp.363-446, 2009.
DOI : 10.1007/s10817-009-9155-4

URL : https://hal.archives-ouvertes.fr/inria-00360768

X. Leroy, Mechanized semantics In Logics and languages for reliability and security, volume 25 of NATO Science for Peace and Security Series D: Information and Communication Security, pp.195-224, 2010.

F. Pfenning and C. Elliott, Higher-Order Abstract Syntax, Proc. PLDI, pp.199-208, 1988.

D. Richards and D. R. Lester, A monadic approach to automated reasoning for Bluespec SystemVerilog, Innovations in Systems and Software Engineering, vol.2, issue.1, pp.85-95, 2011.
DOI : 10.1007/s11334-011-0149-0

M. Sheeran, Hardware Design and Functional Programming: a Perfect Match, J. UCS, vol.11, issue.7, pp.1135-1158, 2005.

K. Slind, S. Owens, J. Iyoda, and M. Gordon, Proof producing synthesis of arithmetic and cryptographic hardware, Formal Aspects of Computing, vol.12, issue.1, pp.343-362, 2007.
DOI : 10.1007/s00165-007-0028-5

A. Slobodová, J. Davis, S. Swords, and W. A. Hunt-jr, A flexible formal verification framework for industrial scale validation, Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011), pp.89-97, 2011.
DOI : 10.1109/MEMCOD.2011.5970515