M. Keating and P. Bricaud, Reuse methodology manual, 1999.
DOI : 10.1007/978-1-4615-5037-2

J. Tomas, Y. Bornat, S. Saighi, T. Levi, and S. Renaud, Design of a modular and mixed neuromimetic ASIC, 2006 13th IEEE International Conference on Electronics, Circuits and Systems, pp.946-949, 2006.
DOI : 10.1109/ICECS.2006.379946

URL : https://hal.archives-ouvertes.fr/hal-00181404

T. Levi, N. Lewis, S. Saighi, J. Tomas, Y. Bornat et al., Neuromimetic Integrated Circuits, 12 in VLSI Circuits for Biomedical Applications, pp.241-264, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00319278

S. Saighi, Y. Bornat, J. Tomas, G. L. Masson, and S. Renaud, A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable, Real-Time, Silicon Neurons, IEEE Transactions on Biomedical Circuits and Systems, vol.5, issue.1, pp.3-19, 2011.
DOI : 10.1109/TBCAS.2010.2078816

URL : https://hal.archives-ouvertes.fr/hal-00562021

A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, C. Petre et al., A Floating-Gate-Based Field-Programmable Analog Array, IEEE Journal of Solid-State Circuits, vol.45, issue.9, pp.1781-1794, 2010.
DOI : 10.1109/JSSC.2010.2056832

H. Koh, C. Sequin, and P. Gray, OPASYN: a compiler for CMOS operational amplifiers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.9, issue.2, pp.113-125, 1990.
DOI : 10.1109/43.46777

R. Phelps, M. Krasnicki, R. Rutenbar, L. Carley, and J. Hellums, Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.6, pp.703-717, 2000.
DOI : 10.1109/43.848091

R. Iskander, Knowledge-aware synthesis for analog integrated circuit design and reuse, Dissertation, 2008.

E. Martens and G. Gielen, High-level modeling and synthesis of analog integrated systems, 2008.
DOI : 10.1007/978-1-4020-6802-7

R. Harjani, R. Rutenbar, and L. R. Carley, OASYS: a framework for analog circuit synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.8, issue.12, pp.1247-1265, 1989.
DOI : 10.1109/43.44506

R. Rutenbar, G. Gielen, and J. Roychowdhury, Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs, Proceedings of the IEEE, 2007.
DOI : 10.1109/JPROC.2006.889371

G. Gielen and R. Rutenbar, Computer-aided design of analog and mixed-signal integrated circuits, Proceedings of the IEEE, pp.1825-1852, 2000.
DOI : 10.1109/5.899053

R. Castro-lopez, F. V. Fernandez, O. Guerra-vinuesa, A. Rodriguez, and . Vasquez, Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits, 2006.

F. De-bernardinis, P. Nuzzo, and A. S. Vincentelli, Robust system level design with analog platforms, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design , ICCAD '06, pp.334-341, 2006.
DOI : 10.1145/1233501.1233569

X. Sun, P. Nuzzo, C. Wu, and A. S. Vincentelli, Contract-based system-level composition of analog circuits, Proceedings of the 46th Annual Design Automation Conference on ZZZ, DAC '09, pp.605-610, 2009.
DOI : 10.1145/1629911.1630066

S. Ohr and L. Marchant, PANEL: analog intellectual property: now? or never?, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), pp.181-182, 2002.
DOI : 10.1109/DAC.2002.1012616

R. J. Koch and F. Dielacher, E1 analog IP - stairway to SoC heaven?, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., pp.1-2, 2003.
DOI : 10.1109/ISSCC.2003.1264002

R. Singh, Analog IP re-use: concerns for " digitally-oriented " SoC designers, EETIMES, vol.1912, 2005.

R. Goering, True Circuits rolls out 65-nm analog IP, EETIMES, vol.12, issue.06, 2006.

Z. Li, L. Luo, and J. Yuan, A Study on Analog IP Blocks for Mixed- Signal SoC, Proceedings ASIC, pp.564-567, 2003.

M. Dessouky, A. Kaiser, M. Louërat, and A. Greiner, Analog design for reuse-case study: very low-voltage ???? modulator, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.353-360, 2000.
DOI : 10.1109/DATE.2001.915049

B. Gilbert, Design for manufacture, Trade-offs in analog circuit design. The designer's companion, 2002.

. Vsia, Analog/Mixed-Signal VSI Extension Specification Version 2.2

J. Michel and F. Schwartz, Analogue circuit sizing method using interval analysis, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, pp.331-334, 2008.
DOI : 10.1109/NEWCAS.2008.4606388

URL : https://hal.archives-ouvertes.fr/hal-00349890

I. O. Connor, F. Tissafi-drissi, G. Révy, and F. Gaffiot, UML/XMLbased approach to hierarchical AMS synthesis, Proceedings FDL 2005, 2005.

I. O. Connor, CNTFET Modeling and Reconfigurable Logic-Circuit Design, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, issue.11, pp.2365-2379, 2007.
DOI : 10.1109/TCSI.2007.907835

URL : https://hal.archives-ouvertes.fr/hal-00187137

I. Connor and A. Kaiser, Automated synthesis of current-memory cells, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.4, pp.413-424, 2000.
DOI : 10.1109/43.838991

URL : https://hal.archives-ouvertes.fr/hal-00158504

R. Castro-lopez, O. Guerra, E. Roca, and F. V. Fernandez, An Integrated Layout-Synthesis Approach for Analog ICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.7, pp.1179-1189, 2008.
DOI : 10.1109/TCAD.2008.923417

M. Hamour, R. Saleh, S. Mirabbasi, and . Ivanov, Analog IP design flow for SoC applications, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.676-679, 2003.
DOI : 10.1109/ISCAS.2003.1206196

J. V. Pimentel, J. C. Da, and . Costa, A Methodology for Describing Analog/Mixed-Signal Blocks as IP, Design&Reuse Articles, 2010.

D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C. Moss, J. M. Rochelle et al., A CAD methodology for optimizing transistor current and sizing in analog CMOS design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22, issue.2, pp.225-237, 2003.
DOI : 10.1109/TCAD.2002.806606

R. Iskander, L. De-lamarre, A. Kaiser, and M. Rosset-louërat, Design space exploration for analog IPS using CAIRO+, International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04., pp.473-476, 2004.
DOI : 10.1109/ICEEC.2004.1374503

URL : https://hal.archives-ouvertes.fr/hal-00140990

R. Iskander, M. Louërat, and A. Kaiser, Automatic DC operating point computation and design plan generation for analog IPs, Analog Integrated Circuits and Signal Processing, vol.43, issue.1, 2008.
DOI : 10.1007/s10470-007-9075-3

URL : https://hal.archives-ouvertes.fr/hal-00356973

F. Tissafi-drissi, I. O. Connor, and F. Gaffiot, RUNE: platform for automated design of integrated multi-domain systems application to high-speed CMOS photoreceiver front-ends, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.16-21, 2004.
DOI : 10.1109/DATE.2004.1269191

A. L. Hodgkin and A. F. Huxley, A quantitative description of membrane current and its application to conduction and excitation in nerve, Journal of Physiology, 1952.

S. Renaud, J. Tomas, N. Lewis, Y. Bornat, A. Daouzli et al., PAX: A mixed hardware/software simulation platform for spiking neural networks, Neural Networks, vol.23, issue.7, pp.905-916, 2010.
DOI : 10.1016/j.neunet.2010.02.006

URL : https://hal.archives-ouvertes.fr/hal-01179647

C. J. Shi and A. Vachoux, VHDL-A Design Objectives And Rationale, Current issues in electronic modeling, pp.1-30, 1995.
DOI : 10.1007/978-1-4615-2333-8_1

F. Pêcheux, C. Lallement, and A. Vachoux, VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.2, 2005.
DOI : 10.1109/TCAD.2004.841071

R. Bowen and K. Coar, Apache server, 2000.

P. Dubois, MySQL, Sams Developer's Library, 2005.

S. Abiteboul, P. Buneman, and D. Suciu, Data on the web from relations to semistructured data and XML, 2000.

T. Levi, J. Tomas, N. Lewis, and P. Fouillat, A CMOS Resizing Methodology for Analog Circuits, IEEE Design & Test of Computers, vol.26, issue.1, pp.78-87, 2009.
DOI : 10.1109/MDT.2009.1

S. Renaud, J. Tomas, Y. Bornat, A. Daouzli, and S. Saïghi, Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks, 2007 IEEE International Symposium on Circuits and Systems, pp.3355-3358, 2007.
DOI : 10.1109/ISCAS.2007.378286

URL : https://hal.archives-ouvertes.fr/hal-00161313

S. Youssef, F. Javid, D. Dupuis, R. Iskander, and M. Louerat, A Pythonbased layout-aware analog design methodology for nanometric technologies, pp.62-67, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00749906