M. Wipliez, Compilation Infrastructure for Dataflow Programs, National Institute of Applied Sciences (INSA) -Rennes, 2010.
URL : https://hal.archives-ouvertes.fr/tel-00598914

N. Siret, M. Wipliez, J. Nezan, and A. Rhatay, Hardware code generation from dataflow programs, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.113-120, 2010.
DOI : 10.1109/DASIP.2010.5706254

URL : https://hal.archives-ouvertes.fr/hal-00565300

G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, vol.26, issue.4, pp.18-25, 2009.
DOI : 10.1109/MDT.2009.83

P. Coussy and A. Morawiec, High-level synthesis: from algorithm to digital circuit, 2008.
DOI : 10.1007/978-1-4020-8588-8

I. Berkeley-design and . Technology, An independent evaluation of: Highlevel synthesis tools for xilinx fpgas, www.BDTI.com, Tech. Rep, 2010.

J. Castillo, P. Huerta, and J. Martínez, An Open-Source Tool for SystemC to Verilog Automatic Translation, Latin American Applied Research, 2007.

P. Coussy, D. Gajski, M. Meredith, and A. Takach, An Introduction to High-Level Synthesis, IEEE Design & Test of Computers, vol.26, issue.4, pp.8-17, 2009.
DOI : 10.1109/MDT.2009.69

URL : https://hal.archives-ouvertes.fr/hal-00447325

M. Mattavelli, I. Amer, and M. Raulet, The Reconfigurable Video Coding Standard [Standards in a Nutshell, IEEE Signal Processing Magazine, vol.27, issue.3, pp.159-167, 2010.
DOI : 10.1109/MSP.2010.936032

URL : https://hal.archives-ouvertes.fr/hal-00488661

M. Wipliez, G. Roquier, and J. Nezan, Software Code Generation for the RVC-CAL Language, Journal of Signal Processing Systems, vol.29, issue.12, 2009.
DOI : 10.1007/s11265-009-0390-z

URL : https://hal.archives-ouvertes.fr/hal-00407950

J. Gorin, M. Wipliez, J. Piat, F. Preteux, and M. Raulet, An LLVM-based decoder for MPEG Reconfigurable Video Coding, 2010 IEEE Workshop On Signal Processing Systems, 2010.
DOI : 10.1109/SIPS.2010.5624767

URL : https://hal.archives-ouvertes.fr/hal-00560029

J. Ashenden and P. , The Designer's Guide to VHDL -third edition, 2008.

R. Megalingam, K. Venkat, S. Vineeth, M. Mithun, and R. Srikumar, Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking, 2009 International Conference on Computer Technology and Development, pp.535-539, 2009.
DOI : 10.1109/ICCTD.2009.195

J. W. Janneck, I. D. Miller, D. B. Parlour, G. Roquier, M. Wipliez et al., Synthesizing Hardware from Dataflow Programs, Journal of Signal Processing Systems, vol.83, issue.5, 2009.
DOI : 10.1007/s11265-009-0397-5

URL : https://hal.archives-ouvertes.fr/hal-00407947

N. Siret, I. Sabry, J. Nezan, and M. Raulet, A codesign synthesis from an MPEG-4 decoder dataflow description, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, pp.1995-1998, 2010.
DOI : 10.1109/ISCAS.2010.5537107

URL : https://hal.archives-ouvertes.fr/hal-00560031